Analitički model za procenu dinamičke potrošnje aritmetičkih kola implementiranih na FPGA
Чланови комисијеLitovski, Vančo
МетаподациПриказ свих података о дисертацији
During the past years the progress of silicon process technology marched on relentlessly. According to Moore’s law, silicon process technology continues improvement at an astonishing pace. Every 2 years the number of transistors that can be integrated on a single IC approximately doubles. The continued scaling of the CMOS technology has led us into the deep submicron regimes where design is not limited by the functionality on a chip but is constrained with its power consumption. Numerous portable battery-powered electronic devices with outstanding performances are the prove of previous statement. Starting from 180nm technologies, static power consumption due to leaky “off” transistors is now a non negligible source of power dissipation, even in running mode. Thus, the total power consumption (i.e. dynamic plus static power) has to be optimized instead of simply reducing dynamic power. The first part of this work is oriented toward the problems of power consumption (both sta...tic and dynamic) minimization techniques. The largest impact on power reduction can be achieved at the system level where architecture and algorithms are to be defined. Influencing power consumption without sacrificing system performances is becoming harder and harder at the lower levels of system design flow. Selecting the most power efficient algorithm out of many available requires a fast and accurate way to estimate the power consumption of any implementation. In this way, time-consuming low-level implementations of each possible design architecture will be avoided. Therefore, the second part of this thesis deals with high-level dynamic power estimation models of DSP-oriented (Digital Signal Processing) designs. This dissertation is the continuation of the work on power estimation models described in [Jev09] and presents the methodology for high-level logic power estimation which is based on the component’s structure and the analytical computation of the switching activity produced inside the component. Power estimation models are parametrized in terms of input signal statistics (mean, variance, autocorrelation) and operands’ word-lengths. The improvement of the existing model for ripple carry array multiplier switching activity (dynamic power) estimation is firstly presented. Unlike previous DBT (Dual-Bit Type) model, the TBT (Triple-Bit Type) model presented here takes into account nonlinearities in bit-level switching activities occurring at the multiplier output. It is experimentally confirmed that the model proposed in this thesis gives far better power estimations (four to five times) than the previous one. After that, the methodology for high-level logic power estimation of binary divider is presented. To the best of author’s knowledge no previous work focuses on high-level divider power estimation. In order to evaluate proposed models, DSP designs are implemented on Virtex II Pro FPGA device on XUP (Xilinx University Program) board and dynamic on-board power consumption is measured. Apart on-board dynamic power, as a reference for our models evaluation, XPower Analyzer tool within the Xilinx ISE software package is used. The mean relative errors of our high-level power estimation models are less than 10% which is very encouraging result, given a fact that the models have high-level nature. In addition to high accuracy, proposed methodology for dynamic power estimation is very fast. The power estimates are obtained in order of milliseconds.