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Napredni metodi projektovanja digitalnih integrisanih kola u nanometarskim tehnologijama sa posebnim naglaskom na brzinu, statičku i dinamičku potrošnju

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2016
Disertacija7463.pdf (2.601Mb)
Jovanovic_Borisav_D.pdf (3.902Mb)
Author
Jovanović, Borisav D.
Mentor
Petković, Predrag
Committee members
Damnjanović, Milunka
Jevtić, Milun
Milovanović, Dragiša
Živanović, Miloš
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Abstract
Advanced methods for digital circuit design, based on modern nanoscale technologies, are applied to a novel SoC microcontroller design with the industry standard 8051 instruction set. The power consumption of the proposed IP cores and the effects of utilization of both static and dynamic power minimization techniques will be examined using following process technologies: CMOS 350 nm, 90 nm and 65 nm. The static power saving methodologies which include shutting down any inactive digital block, reduction of supply voltage and utilization of different standard cell libraries, allows for significant improvements in energy efficiency.
Faculty:
Универзитет у Нишу, Електронски факултет
Date:
03-03-2016
Keywords:
Dynamic and static dissipation power / statička i dinamička snaga disipacije CMOS kola / tehnike za smanjenje snage / mikrokontroler / pouzdanost rada sistema / IP blok / low power techniques / microcontroller / faulttolerances / IP block
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Handle
https://hdl.handle.net/21.15107/rcub_nardus_7455
URI
http://eteze.ni.ac.rs/application/showtheses?thesesId=4513
https://nardus.mpn.gov.rs/handle/123456789/7455
https://fedorani.ni.ac.rs/fedora/get/o:1242/bdef:Content/download
http://vbs.rs/scripts/cobiss?command=DISPLAY&base=70052&RID=533864854

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