Napredni metodi projektovanja digitalnih integrisanih kola u nanometarskim tehnologijama sa posebnim naglaskom na brzinu, statičku i dinamičku potrošnju

Abstract

Advanced methods for digital circuit design, based on modern nanoscale technologies, are applied to a novel SoC microcontroller design with the industry standard 8051 instruction set. The power consumption of the proposed IP cores and the effects of utilization of both static and dynamic power minimization techniques will be examined using following process technologies: CMOS 350 nm, 90 nm and 65 nm. The static power saving methodologies which include shutting down any inactive digital block, reduction of supply voltage and utilization of different standard cell libraries, allows for significant improvements in energy efficiency.