Pojačavači snage u klasi A sa istovremenim konjugovanim prilagođenjem i prilagođenjem po snazi pri velikim signalima na izlaznom pristupu

Abstract

Disertacija se bavi razvojem metodologije projektovanja i unapre enjem topologija pojacavaca snage u klasi A sa istovremenim konjugovanim prilago enjem i prilago enjem po snazi pri velikim signalima na izlaznom pristupu. Jedan od osnovnih zahteva za svaki pojacavac snage jeste efikasnost. U slucaju pojacavaca snage u klasi A, tranzistor treba prilagoditi po snazi pri velikim signalima na izlaznom pristupu da bi se opterecenju predala maksimalna moguca snaga. Osim prilago enja po snazi, pojacavaci male i srednje snage cesto moraju biti i konjugovano-kompleksno prilago eni na izlaznom pristupu. Ovaj zahtev je bitan pošto je uobicajeno da je sledeci stepen projektovan tako da optimalno radi kada je konjugovano-kompleksno prilago en na ulaznom pristupu. Pojacavaci male i srednje snage su obicno implementirani u standardnoj complementary metal-oxide semiconductor (CMOS) tehnologiji, dok naredni stepen može biti filtar za potiskivanje neželjenih harmonika ili pojacavac snage napravljen u nekoj od III-V generacija poluprovodnicke tehnologije sa znatno vecom izlaznom snagom. Standardni pojacavac sa zajednickim sorsom može biti prilago en po snazi pri velikim signalima ili konjugovano prilago en na izlaznom pristupu, ali se oba prilago enja ne mogu, u opštem slucaju, ostvariti istovremeno. Da bi se prevazišlo pomenuto ogranicenje, predložena je topologija pojacavaca sa drejn-gejt povratnom spregom kao i kompletna metodologija projektovanja. U svrhu verifikacije razvijene teorije, projektovan je širokopojasni pojacavac snage u 130 nm RFCMOS tehnologiji. Postignuta je maksimalna izlazna snaga od 7 dBm i efikasnost od 20%, u opsegu ucestanosti od 6 do 9 GHz. Koeficijent refleksije na ulaznom i izlaznom pristupu je manji od -8,5 dB i -9,5 dB, redom.

The dissertation deals with the development of design methodology and the enhancement of topology of power amplifiers in class A with simultaneous conjugate and power matching for large signals at the output port. One of the major demands for any power amplifier is power efficiency. In the case of a power amplifier in Class A, the transistor needs to be power matched for large signals at the output port in order to deliver maximum power to the load. This criterion is particularly important in the case of an amplifier with an output power of the order of 30 dBm or more. In addition to power matching, small and medium power amplifiers often have to be conjugately matched at the output port as well. This requirement is important because it is quite common that the next stage is designed so that it works optimally when it is conjugately matched at the input port. Small and medium power amplifiers are usually implemented in standard complementary metal-oxide semiconductor CMOS technology, while the next stage can be a filter for suppressing unwanted harmonics or a power amplifier made in one of the III-V generations of semiconductor technology with significantly higher output power. A standard common-source amplifier can be designed to be either large signal power matched or conjugately matched at the output port, but not both of them at the same time. In order to overcome the mentioned limit, we propose a simple topology based on a drain-gate feedback amplifier, together with a complete design methodology. For the purpose of verifying the developed theory, a broadband power amplifier is designed in 130 nm RFCMOS technology. The amplifier achieves 7 dBm peak output power and maximum power efficiency of about 20% in the frequency range from 6 to 9 GHz. Input and output return loss are better than 8.5 and 9.5 dB, respectively.