Metodi projektovanja monolitnih mikrotalasnih integrisanih kola predviđenih za rad sa signalima učestanosti oko 60 GHz

Abstract

Potreba za bežicnim komunikacioniom linkovima velikih brzina prenosa podataka je podstaknuta ekspanzijom prenosivih uređaja i multimedijalnih servisa, uz pogodnost da priroda korišcenja dozvoljava a ponekad i zahteva ogranicen domet. Problem kapaciteta komunikacionih linkova i sve veceg broja korisnika se može rešiti prelaskom u opseg ucestanosti od 30 do 300 GHz, koji se naziva i milimetarski opseg. Visoka radna ucestanost pruža mogucnost korišcenja kanala velikog kapaciteta, kao i fizicki malih antenskih nizova za fokusiranje i prostornu lokalizaciju prijemnog i predajnog snopa. Milimetarski opseg nalazi primene i u ostalim oblastima, kao što su industrijske, medicinske i bezbednosne. U komercijalnim primenama od interesa je opseg ucestanosti oko 60 GHz, koji je dodeljen za nelicenciranu upotrebu širom sveta. Razvoj CMOS i BiCMOS tehnologija je omogucio da se sistemi u 60 GHz-om opsegu mogu integrisati u standardnim procesima. Pored viših radnih ucestanosti, skaliranje tehnologija uvodi i tehnološka ogranicenja koja degradiraju performanse ukoliko se njihov uticaj zanemari. Zanemareni efekti mogu doprineti vecim gubicima, koji povecavaju faktor šuma prijemnika i degradiraju efikasnost predajnika, ali i parazitnim preslušavanjima koja rezultuju neželjenim spektralnim komponentama. Stoga je potrebno razmotriti kvalitativne i kvantitativne pokazatelje uticaja tehnoloških ogranicenja na performanse i prilagoditi postupak projektovanja. Kriticni blokovi za domet primopredajnika su malošumni pojacavac na prijemnoj strani i pojacavac snage na predajnoj strani. U okviru teze predstavljen je postupak projektovanja malošumnog pojacavaca i pojacavaca snage za rad u 60 GHz-om opsegu i širokopojasnog delitelja ucestanosti. Uvedene su nove smernice projektovanja koje uzimaju u obzir tehnološka ogranicenja. Pokazano je da se pravilnim particionisanjem elektromagnetskog modela može postici dobro slaganje rezultata simulacije i merenja. Projektovana kola su fabrikovana u IHP Microelectronics korišcenjem 0.25 mm SiGe:C BiCMOS procesa (fT/fmax = 200 GHz). Parametri fabrikovanih kola su izmereni i verifikovani na stopicama cipa, upotrebom mikrotalasnih sondi...

The need for high capacity wireless data links is driven by expansion of mobile devices and multimedia services, with the advantage that a typical use case allows, and sometimes demands, a limited range. Problems of limited communication link capacity and growing number of users can be solved by moving to frequency range of 30 - 300 GHz, also known as millimeter range. High operating frequency allows the use of high capacity channels, and physically small antenna arrays for beam steering and spatial localization. Millimeter region of spectrum is also suitable for industrial, scientific and security applications. Unlicensed 60 GHz band is available worldwide, and is attractive for commercial applications. Development of CMOS and BiCMOS technologies has enabled the integration of complete 60 GHz systems in standard processes. Technology scaling enables the use of higher operating frequencies, but imposes new design constraints which may degrade the performance if their effect is neglected. Neglected effects may contribute to higher losses, which increase the noise figure of receiver and degrade transmitter efficiency, and also to parasitic coupling which results in undesired spectral components. Therefore, qualitative and quantitative measure of technology constraints impact on performance degradation needs to be evaluated, and applied to circuit design process. Critical blocks for transceiver range are low noise amplifier on receiver, and power amplifier on transmitter side. Design procedures for 60 GHz low noise and power amplifiers, and wideband frequency divider are presented in this thesis. Guidelines for technology constraints aware design are used in the presented design flow. Good agreement of experimental and simulation results is achieved by proper electromagnetic model partitioning. Designed circuits have been fabricated in IHP Microelectronics 0.25 mm SiGe:C BiCMOS process (fT/fmax = 200 GHz). Test chip parameters have been measured and verified on-wafer by using microwave probes...